The present invention relates to a hybrid LSI (large scale integrated circuit) having CMOS (complementary metal oxide semiconductor) transistors and bipolar transistors formed on a common substrate and, in particular, to structures of gate electrodes of the MOS transistors and emitter electrodes of the bipolar transistors and a method of fabricating them.
Recently, attention has been given to a BiCMOS technology. The BiCMOS technology is used for forming bipolar transistors, capable of controlling the large current, and CMOS transistors, suitable for high-level integration, on the same chip. The BiCMOS technology is known as a method of achieving low-level voltage and acceleration of the LSI including digital and analog circuits. However, in the BiCMOS technology, since the bipolar transistors and the CMOS transistors are formed on the same chip, the number of processes is likely to cause increase in fabrication cost.
In view of this, various proposals have been made for reducing the number of fabrication processes, for example, as disclosed in a paper entitled "An Advanced Single-Level Polysilicon Submicrometer BiCMOS Technology" by Michael P. Brassington et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 36, No. Apr. 4, 1989, pp. 712-719.
One of the proposals will be described hereinbelow.
An n-type epitaxial layer is first grown on a silicon substrate of a p conductivity type which is formed in advance with n.sup.+ buried layers and p.sup.+ buried layers. Then, using the LOCOS (local oxidation of substrate) method, field oxidized films are formed. Subsequently, n-type well regions, p-type well regions, .sup.+ n -type collector leading regions and base regions of bipolar transistors are formed. Then, just after formation of gate oxidized films, each in a thickness of 50 to 200 angstroms, of NMOS and PMOS transistors, a polysilicon layer is grown to a thickness of 500 to 1,000 angstroms. This polysilicon layer is provided for preventing a problem, such as a resistance failure of the gate oxidized films due to contamination or damage thereof in a subsequent process of forming emitter contacts.
Subsequently, the polysilicon layer and the gate oxidized film at emitter regions of the bipolar transistors are etched to form the emitter contacts, and then another polysilicon layer is deposited to a thickness of 1,000 to 2,000 angstroms over the whole area.
Subsequently, the upper and lower polysilicon layers are etched to form gate electrodes of the NMOS transistors, gate electrodes of the PMOS transistors and emitter electrodes of the bipolar transistors. Thereafter, an oxidized film is deposited to a thickness of 1,000 angstroms, and then anisotropic dry etching is performed so as to form sand walls on the sides of each of the gate electrodes and the emitter electrodes. Subsequently, boron is doped through ion implantation at concentration of 5.times.10.sup.15 cm.sup.-2 to 7.times.10.sup.15 cm.sup.-2 into source and drain regions and the gate electrodes of the PMOS transistors and external base regions of the bipolar transistors. On the other hand, arsenic is doped through ion implantation at concentration of 1.times.10.sup.16 cm.sup.-2 to 2.times.10.sup.16 cm.sup.-2 into source and drain regions and the gate electrodes of the NMOS transistors and the emitter electrodes. Thereafter, the heat treatment is applied in the nitrogen atmosphere at 850 to 900.degree. C. so as to activate the implanted impurities. Then, at the gate electrodes of the PMOS transistors, boron diffuses from the upper polysilicon layers into the lower polysilicon layers so that the p-type gate electrodes are formed. On the other hand, at the gate electrodes of the NMOS transistors, arsenic diffuses from the upper polysilicon layers into the lower polysilicon layers so that the n-type gate electrodes are formed. Further, at the emitter electrodes of the bipolar transistors, arsenic diffuses from the upper polysilicon layers into the n-type epitaxial layer so that emitter regions of the bipolar transistors are formed.
In the foregoing conventional example, the gate electrodes and the emitter electrodes are formed by the same polysilicon two-layers, respectively, the source and drain regions of the PMOS transistors and the external base regions of the bipolar transistors are formed through the same process, and the source and drain regions of the NMOS transistors and the emitter electrodes of the bipolar transistors are formed through the same process, so as to achieve simplification of the fabrication processes.
However, the semiconductor device thus fabricated and the fabrication method thereof have the following problems.
At the p-type gate electrode of the PMOS transistor, boron implanted into the upper polysilicon layer and diffused into the lower polysilicon layer further diffuses into the silicon substrate via the gate oxidized layer (known boron punch-through). This may cause dispersion of threshold voltages of the PMOS transistors. Further, the as boron punch-through is accelerated depending on the heat treatment atmosphere or temperature, or presence of fluorine in polysilicon. Thus, the fabrication process after introduction of boron into the gate electrode may be limited in various ways.
Further, since formation of a resist mask and removal of the resist mask are required in the process of forming the emitter contact after formation of the lower polysilicon layer, a spontaneous oxidized thin film is formed on the surface of the lower polysilicon layer. This oxidized film causes the following disadvantage onto the NMOS transistor. Specifically, the oxidized film works as a barrier when the impurities doped into the upper polysilicon layer of the gate electrode diffuse into the lower polysilicon layer. Thus, the oxidized film prevents uniform redistribution of the impurities into the upper and lower polysilicon layers so that the impurity concentration in the lower polysilicon layer is lowered. When the impurity concentration in the lower polysilicon layer is low, a depletion layer expands in the lower polysilicon layer upon application of the voltage across the gate electrode to turn on the NMOS transistor. Thus, a channel is not fully formed in the silicon substrate so that the characteristic of the NMOS transistor is lowered. On the other hand, at the emitter portion of the bipolar transistor, the impurities are prevented from fully diffusing from the lower polysilicon layer near the emitter contact into the emitter region so that the so-called plug effect becomes significant to reduce the impurities around the emitter contact. This lowers the current amplification factor and increases the emitter resistance.